Aldec Releases its Desktop Master Design and Analysis ToolHenderson Nevada, May 13th, 2002 -- Aldec, Inc., a pioneer in mixed language simulation and advanced design tools for FPGA devices, announced today the release of Desktop Master. Derived from Aldec’s Active-HDL, a completely integrated design entry and verification product, Desktop Master includes advanced graphical design entry tools, an IP Core Generator and a simulation Waveform Viewer in order to support the growing number of design teams that prefer to enter designs on a PC and run simulation tasks on a Workstation.
Desktop Master works directly with all leading FPGA products and includes graphical gate level primitives for most FPGA vendors. Desktop Master also seamlessly imports EDIF schematics for their use in an HDL environment.
“Because design functions have moved towards networks and design teams, there is now a greater differentiation between design job functions than there previously was. Some team members now concentrate exclusively on design entry and analysis, and these activities can now be supported with lower cost tools such as Desktop Master software,” stated Megan Moran, Product Marketing Manager for Active-HDL.
Graphical Entry Tools
Desktop Master provides users with the most advanced FPGA design entry tool on the market. The tool contains Aldec’s industry-proven HDL Text Editor, Block Diagram Editor, State Machine Editor, IP Core Generator and Waveform Viewer.
The HDL Editor incorporates several advanced features for coding and scripting. The product also includes a Language Assistant, which aids in HDL source code development by inserting frequently used code directly into the design from a pre-defined or user-defined template. Desktop Master’s HDL Editor supports VHDL, Verilog and Perl code.
The graphical Block Diagram Editor allows the designer to access the lower levels of the design hierarchy with the simple click of a mouse, which shows the components that are comprised within that section. Users can also cross-probe a section of the Block Diagram to its respective HDL Code. The Block Diagram Editor can generate HDL code that contains only the architecture body for use in different design implementations. All standard Microsoft OLE functions are supported to aid in the documentation of the design.
The State Machine Editor generates bubble diagrams in place of traditionally modeled sequential devices, allowing users to easily retarget any device and specify the port properties of each machine. The State Machine Editor supports the creation of asynchronous state machines and can convert a diagram to a hierarchal state so that a very complex state machine may be dissected into discrete modules and be easier to document. HDL code is automatically generated after the FSM’s compilation for additional cross-probing functions. Multi-process VHDL code templates are supported and states can easily be modified.
All graphical design entry tools can generate HDL files in either VHDL or Verilog. The file structure and hierarchy are maintained in the Design Browser and can be merged into one complete HDL file for simulation.
IP Core Generation
The IP Core Generator gives designers access to the most extensively tested and proven IP Cores in the industry. Each IP core that is included in Desktop Master has been previously tested and verified in hardware. IP modules can be customized in the Desktop Master tool, providing extended functionality to support users’ specific design requirements.
Instead of supplying a black box module without a VHDL or Verilog description, the IP Core Generator creates the HDL code so that designers can see how it is written for use in other segments of their design. Prior to generating the HDL code, the IP Core Generator supplies the user with options to either generate a Block Diagram or macro file and to compile each file after its generation. Such directives give users maximum design latitude for their use of IP Cores.
Remote Simulation for Team-Based Design
Once the design has been developed, it can be sent to a remote computer to perform simulation, synthesis and other design functions. Desktop Master users can view the simulation results directly on their PCs, without the need for supplemental software applications. Since Desktop Master uses Active-HDL’s highly integrated GUI, users can automatically launch various support tools that are needed in the FPGA design process.
Integrated Revision Control
Desktop Master includes support for all leading Revision Control systems. All design files can be checked in and out, and referenced as either read-only or write/read files to help with the use of multiple HDL source files and IP Cores for all design team members.
With many of the design verification applications residing on network servers for team-based designs, EDA tools often require only design entry and post-simulation data analysis. Desktop Master software has been tailored to serve both functions so that users can benefit from a network environment. Desktop Master is aimed at the most popular design activities such as design entry and simulation analysis and comes at a nominal cost to the user.
Availability
Active-HDL’s Desktop Master supports mixed VHDL and Verilog design entry and can be purchased in either a node lock or floating license configuration. All sales include one year of product maintenance. Active-HDL runs on Windows 98/2000/NT and XP platforms and includes an FPGA Design Flow Manager, HDL Editor, Block Diagram Editor, FSM Editor and Waveform Viewer. To receive your FREE evaluation copy of Desktop Master, contact Aldec at 702.990.4400 or visit www.aldec.com.
About Aldec
Aldec, Inc., an 18-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs. It is recognized that to be productive in today’s market and to best serve customers in the future, new technologies and innovations that go beyond traditional methods of conducting business in the EDA industry must be pursued. Aldec is committed to customer service and is actively developing a company that will evolve along with its customers’ designs. Additional information about Aldec is available at http://www.aldec.com.
Active-HDL is a trademark of Aldec, Inc. All other trademarks or registered
trademarks are property of their respective owners
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Contact: Megan Moran
Aldec, Inc.
(702) 990-4400 ext. 201
meganm@aldec.com
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